This invention relates generally to semiconductor chips electrically and mechanically connected to a substrate, particularly to flip-chip configurations.
Flip-chip technology is well known in the art. FIG. 1 illustrates a semiconductor chip having solder bumps formed on the active side of the semiconductor chip 100 that is inverted and bonded to a substrate 101 through the solder joints 102 by reflowing solder to wet metallized pads 106. Structural solder joints 102 are formed from solder bumps situated between the semiconductor chip and the substrate to form the mechanical and electrical connections between the chip and substrate. A narrow gap 103 is left between the semi-conductor chip and the substrate.
One obstacle to flip-chip technology when applied to polymer printed circuit substrates (i.e., circuit boards) is the unacceptably poor reliability of the solder joints due to the mismatch of the coefficients of thermal expansion of the (i) chip, which typically has a coefficient of thermal expansion of about 3 ppm/xc2x0 C., (ii) the polymer substrate, e.g. epoxy-glass, which has a coefficient of thermal expansion of about 16 to 26 ppm/xc2x0 C., and (iii) the solder joint which has a coefficient of thermal expansion of about 25 ppm/xc2x0 C. As shown in FIGS. 2 and 3, as the flip chip 100 and printed circuit substrate 101 undergo thermal excursions, the substrate expands and contracts at a greater rate than does the chip. (This occurs, for example, in electronic components that are switched on and off.) Because the chip and substrate are stiffer than the solder joints 104, the solder joints are flexed and distorted since they are constrained only by their attachment at both ends by the substrate and chip. The air gap 103 between the chip and the substrate allows these two parts to expand and contract at relatively different rates thereby distorting the solder joints. As the chip and substrate are thermally cycled through normal use, this flexing and bending weakens the solder joints which causes them to quickly fail.
In the past, the problem of solder joint fatigue life in flip-chip/substrate interconnects was addressed by several methods. A typical approach, which is described in U.S. Pat. No. 5,801,449, involves positioning an interposer made of flexible circuitry between the chip and the solder joints. The flex circuit undergoes expansion and contraction without distorting the solder joints despite the presence of the air gap around the solder joints.
As illustrated in FIG. 4, another approach to fatigue life involves underfilling the air gap between the chip and the substrate completely with a solid underfill encapsulant material 104 that consists of a composite of polymer and an inorganic filler and that has a thermal expansion of 20-30 ppm/xc2x0 C. and an elastic modulus of 2-20 GPa. The underfill composite material is typically dispensed around two adjacent sides of the semiconductor chip after the chip 100 has been soldered to the substrate 101. The underfill composite material 104 slowly flows by capillary action to fill the gap between the chip and the substrate. The underfill material is then hardened by baking for an extended period. Underfilling the chip with a subsequently cured encapsulant has been shown to reduce solder joint fatigue failure caused by thermal expansion mismatch between the chip and the substrate. For the underfill encapsulant to be effective, it is important that it adheres well to the chip 100 and the substrate 101. Unlike the previous interposer methods, there cannot be an air gap or separation between the underfill 104 and the chip 100 or the substrate 101. The cured encapsulant reduces the fatigue cycling of the solder joints by virtue of the relative stiffness, or high modulus, of the underfill material in conjunction with the strong solid contact made between the underfill material, the semiconductor chip, the solder joints, and the underlying printed circuit.
As illustrated further in FIGS. 5 and 6, since the solid underfill composite 104 fills the entire gap between the chip 100 and the substrate 101, and since it has a thermal expansion coefficient that is close to that of the solder 102, the substrate and chip no longer expand and contract independently of each other. Instead the relatively larger expansion and contraction of the substrate relative to the chip is constrained by the underfill 104 which is rigidly adhered to both; this also causes the entire assembly to bulge upwards as the temperature is decreased or downwards as the temperature is increased. This bulging effect essentially keeps the relatively fragile solder joints encased solidly in the underfill, and prevents them from appreciably distorting. The result is a large reduction in solder joint fatigue. The hardened, gap-free encapsulant transforms the expansion and contraction forces of the substrate that are induced by temperature changes, into bulging of the entire assembly, which virtually eliminates distortion of the solder joints. The bulging reduces the fatigue of the solder joints and virtually eliminates solder fatigue failure. As a result, the underfilled flip chip assembly solder joint lifetime is greatly increased relative to that of an air gap flip chip solder joint.
The underfilling process, however, makes the assembly of encapsulated flip-chip printed wire boards a time consuming, labor intensive and expensive process with a number of uncertainties. The process involves first applying a soldering flux, generally a no-clean, low residue flux, to the solder bumps on the chip. Then the chip is placed on the substrate. The assembly is subsequently subjected to a solder reflowing thermal cycle whereby the solder melts and joins the chip to the substrate under the action of the soldering flux. The surface tension of the solder aids to self-align the chip to the substrate terminals. After reflow, due to the close proximity of the chip to the substrate, removing any remaining flux residues from under the chip is such a difficult operation that it is generally not done. Yet these residues are known to reduce the reliability and integrity of the subsequent underfill encapsulant.
After soldering, underfill encapsulation of the chip generally follows. In the prior art, as described, for example, in U.S. Pat. No. 5,880,530, the polymers of choice for the underfill encapsulation have been epoxy resins. The thermal expansion coefficients and elastic moduli of the resins can be reduced by the addition of inorganic fillers, such as silica or alumina. To achieve optimum reliability, a coefficient of thermal expansion in the vicinity of 20-30 ppm/xc2x0 C. and an elastic modulus of 2 to 20 Gpa are preferred. Since the preferred epoxies have coefficient of thermal expansion exceeding 80 ppm/xc2x0 C. and elastic moduli of 0.01-2 GPa, the inorganic fillers selected generally have much lower coefficient of thermal expansions and much higher moduli so that, in the aggregate, the epoxy-inorganic mixture is within the desired range for these values. Typically, the filler to resin volume ratio is in the range of 50 to 65%, but this high filler concentration tends to make the resin mixture very viscous, which slows the rate at which it can flow into the gap between chip and substrate during underfilling. Consequently, the slow underfill process is expensive to perform in a large throughput manufacturing environment.
The underflling encapsulation techniques of the prior art have at least five principal disadvantages:
1. The reflowing of the solder bump and subsequent underfilling and curing of the encapsulant is an inefficient multi-step process.
2. Underfilling a flip-chip assembly is time consuming because the viscous resin material must flow through the tiny gap between the chip and the substrate.
3. Air bubbles can be trapped in the underfill encapsulant during the underfilling process and these bubbles later become sites for solder joint failure.
4. The flux residues remaining in the gap reduce the adhesive and cohesive strengths of the underfill encapsulating adhesive, thereby adversely affecting the reliability of the assembly.
5. For larger chips, the limiting effect of capillary action becomes more critical and makes the underflling procedure more time consuming and more susceptible to void formation and to the separation of the polymer from the fillers during underfilling.
U.S. Pat. No. 5,128,746 describes a prior art method for underfill encapsulation of a chip and substrate assembly whereby a liquid polymer encapsulant, which includes a fluxing agent but no inorganic fillers, is applied to the chip or substrate prior to assembly. As shown in to FIGS. 7 and 8, prior to solder reflow, the liquid encapsulant 109 is applied to completely fill the gap between chip and substrate, and engulf the solder bumps 108. This allows the chip 100 to be positioned on the substrate 101 with the liquid polymer flux 109 situated in between. Then, as shown in FIG. 9, the solder bumps 108 are reflowed during which process the flux in the liquid encapsulant promotes wetting of the molten solder to the metallized pads 106 on the substrate as the solderjoints or interconnections 102 are formed and the chip self-aligns to the metallized pads. The polymer in the liquid encapsulant cures during the reflow step and hardens to produce mechanical interconnection 110 located between the substrate and chip and to encapsulate the solder joints 102.
One advantage of this technique is that the reflow and underfilling steps are combined into one, thereby eliminating the slow underfill operation since the encapsulating underfill is applied prior to assembly. However, the chief limitation of this technique is that in order for the molten solder to readily wet the substrate metallized pads and to allow the solder, through surface tension, to self-align the chip to the substrate metallized pads, the polymer flux encapsulant must have a very low viscosity during the reflow step. However, the viscosity of the material is severely increased by the presence of inorganic fillers above a concentration of more that a few percent. As a result, the thermal expansion coefficients of these unfilled polymer flux encapsulant materials are much larger than 20-30 ppm/xc2x0 C. and the elastic moduli are less than 2 GPa. This approach fails to produce an underfill encapsulant material that can serve as both the flux and the encapsulant with the required low coefficient of thermal expansion and high modulus needed for optimum reliability.
The art is in need of a method to pre-apply an underfill encapsulant containing the required inorganic fillers to fill completely the gap between the chip and substrate in such a way that the coefficient of expansion of the material in the gap is near that of the solder, 25 ppm/xc2x0 C., and the modulus is at least 2 GPa.
The present invention is based in part on the discovery of employing a multilayer underfill encapsulant that comprises at least first and second portions or layers, at least one of which comprises a polymer flux. The use of two or more layers allows the layers to have different physical properties as measured by their thermal expansion coefficients and elastic moduli. Electrical components such as flip-chips employing the inventive layers have superior structural integrity. Since the polymer flux generally has a coefficient of expansion exceeding 30 ppm per degree C., this multilayer approach allows the use of polymer fluxes without adversely affecting reliability at the final assembly.
In one aspect, the invention is directed to an electrical component assembly that includes:
(a) a substrate having a substrate surface with a plurality of pads thereon;
(b) an integrated circuit chip having an active surface with a plurality of contacts thereon wherein the substrate surface faces the active surface; and
(c) an encapsulant interposed between substrate and the integrated circuit chip wherein the encapsulant comprises at least two layers including a first layer comprising a polymer or polymer composite having a coefficient of thermal expansion of about 30 ppm/xc2x0 C. or less and an elastic modulus of at least 2 Gpa, and a second layer comprising a polymer flux wherein the encapsulant defines a plurality of channels that are filled with solder and wherein each channel extends from a contact on the active surface to a pad on the substrate surface.
In another aspect, the invention is directed to a method for making an electrical component assembly that includes the steps of:
(a) providing an integrated circuit chip having an active surface with a plurality of contacts thereon and having discrete solder bumps on the plurality of contacts;
(b) coating the active surface of the integrated circuit chip having separate discrete solder bumps thereon with a first encapsulant layer that comprises a liquid polymer resin mixed with inorganic powder wherein the first encapsulant layer after being cured has a coefficient of thermal expansion of about 30 ppm/xc2x0 C. or less and an elastic modulus of at least about 2 GPa;
(c) providing a printed circuit substrate having a substrate surface with a plurality of discrete metallized pads thereon;
(d) coating the printed circuit substrate with a second encapsulant layer comprising a liquid polymer flux;
(e) placing the coated integrated circuit chip on the coated substrate whereby the first and second encapsulant layers are in contact with each other and thereafter causing the solder bumps to penetrate into the second encapsulant layer;
(f) curing the first and second encapsulant layers; and
(g) simultaneously reflowing the solder bumps to electrically connect the contacts of the integrated circuit chip to the pads of the substrate.
In yet another aspect, the invention is directed to a method for making an electrical component assembly that includes the steps of:
(a) providing an integrated circuit chip that has an active surface with a plurality of contacts thereon and having discrete solder bumps on the plurality of contacts;
(b) coating the active surface of the integrated circuit chip having separate discrete solder bumps thereon with a hardened first encapsulant layer comprising a polymer resin and an inorganic filler wherein the first encapsulant layer after being cured has a coefficient of thermal expansion of 30 ppm/xc2x0 C. or less and an elastic modulus greater than 2 GPa;
(c) partially exposing tips of the solder bumps;
(d) coating the first encapsulant with a second encapsulant layer comprising a liquid polymer flux;
(e) providing a printed circuit substrate having a substrate surface with discrete metallized pads thereon;
(f) placing the coated integrated circuit chip on the substrate and thereafter causing the solder bumps tips to penetrate into the second encapsulant layer;
(g) curing the first and second encapsulant layers; and
(h) simultaneously reflowing the solder bumps to electrically connect the contacts of integrated circuit chip to the pads of the substrate.
In still another aspect, the invention is directed to a method for making an electrical component assembly that includes the steps of:
(a) providing an integrated circuit chip having an active surface with a plurality of contact pads thereon;
(b) coating the active surface of the integrated circuit chip with a first encapsulant layer that after being cured has a coefficient of expansion of about 30 ppm/xc2x0 C. or less and an elastic modulus greater than about 2 GPa;
(c) removing portions of the first encapsulant layer to form holes that expose the contact pads on the active surface of the integrated circuit chip;
(d) filling the holes with solder;
(e) coating the first encapsulant layer with a second encapsulant layer that comprises a polymer flux;
(f) placing the integrated circuit chip on a substrate having a substrate surface with a plurality of metallized pads thereon with the first and second encapsulant layers located between the integrated circuit chip and the substrate;
(g) curing the second encapsulant layer; and
(h) simultaneously reflowing the solder to electrically connect the contact pads of the integrated circuit chip to the metallized pads of the substrate.
In still another aspect, the invention is directed to a method for making an electrical component assembly that includes the steps of:
(a) providing a printed circuit board substrate having a substrate surface with a plurality of metallized pads thereon;
(b) coating the metallization pads with a first encapsulant layer that has a coefficient of expansion of about 30 ppm/xc2x0 C. or less and an elastic modulus of greater than about 2 GPa;
(c) removing portions of the first encapsulant layer to form holes that expose the metallization pads;
(d) filling the holes with solder;
(e) coating the first encapsulant layer with a second encapsulant layer that comprises a polymer flux;
(f) placing an integrated circuit chip having an active surface with a plurality of contact pads thereon on the substrate with the first and second encapsulant layers located between the integrated circuit chip and the substrate;
(g) curing the second encapsulant layer; and
(h) simultaneously reflowing the solder to electrically connect the contact pads of the integrated circuit chip to the metallized pads of the substrate.
The semiconductor chip package structures of the present invention provide, among other advantages, simple chip placement followed by reflow without labor intensive underfill steps; a solder bumped chip or substrate with an encapsulant pre-attached, with the encapsulant performing a mechanical function and the solder performing an electrical function; a low-cost method for applying the solder bumps to a flip chip or flip chip substrate by creating holes in a pre-coated encapsulant; and a pre-coated chip encapsulant of two or more layers, with each layer performing a distinct function.